Bizarre Patents
A small umbrella which may be removably attached to a beverage container in order to shade the beverage container from the direct rays of the sun.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120131419 | MEMORY APPARATUS AND METHOD USING ERASURE ERROR CORRECTION TO REDUCE POWER CONSUMPTION Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data ... | 05/24/2012 |
| 20120131261 | SUB-BLOCK ACCESSIBLE NONVOLATILE MEMORY CACHE Subject matter disclosed herein relates to sub-block accessible cache memory.... | 05/24/2012 |
| 20120127807 | MEMORY INSTRUCTION INCLUDING PARAMETER TO AFFECT OPERATING CONDITION OF MEMORY Subject matter disclosed herein relates to techniques to operate memory.... | 05/24/2012 |
| 20120127685 | STACKED PACKAGED INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and se... | 05/24/2012 |
| 20120127674 | SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING ELONGATED FASTENERS Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semicon... | 05/24/2012 |
| 20120126885 | DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a s... | 05/24/2012 |
| 20120126884 | DOUBLE GATED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME A semiconductor device is provided that includes a fin having a first upper gate on a sidewall of the fin in a first trench and a second upper gate formed on the opposite sidewall of the fin. The device also includes a first lower gate on the sidewall and a second lower... | 05/24/2012 |
| 20120126386 | ELECTRONIC DEVICES Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an im... | 05/24/2012 |
| 20120126338 | CROSS-HAIR CELL DEVICES AND METHODS FOR MANUFACTURING THE SAME Systems and methods are disclosed for manufacturing grounded gate cross-hair cells and standard cross-hair cells of fin field-effect transistors (finFETs). In one embodiment, a process may include forming gate trenches and gates on and parallel to row trenches in a subs... | 05/24/2012 |
| 20120110368 | DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough... | 05/03/2012 |
| 20120110246 | EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the me... | 05/03/2012 |
| 20120110244 | COPYBACK OPERATIONS Methods and systems for copyback operations are described. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the me... | 05/03/2012 |
| 20120109896 | DATA SIGNAL MIRRORING Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data ... | 05/03/2012 |
| 20120108069 | METHODS OF FORMING AN INTEGRATED CIRCUIT WITH SELF-ALIGNED TRENCH FORMATION Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. F... | 05/03/2012 |
| 20120108037 | METHODS OF FORMING A PHASE CHANGE MATERIAL A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at le... | 05/03/2012 |
| 20120108033 | METHOD OF MANUFACTURING DEVICES HAVING VERTICAL JUNCTION EDGE Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilic... | 05/03/2012 |
| 20120108010 | STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING STACKED MICROELECTRONIC DEVICES Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on ... | 05/03/2012 |
| 20120106248 | NON-VOLATILE MULTILEVEL MEMORY CELLS The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell ca... | 05/03/2012 |
| 20120104550 | HIGH ASPECT RATIO CONTACTS A contact formed in accordance with a process for etching a insulating material to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating material to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations the... | 05/03/2012 |
| 20120104488 | DATA CELLS AND CONNECTIONS TO DATA CELLS Disclosed are devices, among which is a device that includes a transistor and a contact. The transistor includes two terminals that may be formed in respective legs. The contact includes a first portion extending vertically, and a second portion extending perpendicularl... | 05/03/2012 |
| 20120104347 | METHOD OF FORMING A CHALCOGENIDE MATERIAL, METHODS OF FORMING A RESISTIVE RANDOM ACCESS MEMORY DEVICE INCLUDING A CHALCOGENIDE MATERIAL, AND RANDOM ACCESS MEMORY DEVICES INCLUDING A CHALCOGENIDE MATERIAL A method of forming a chalcogenide material on a surface of a substrate comprising exposing a surface of a substrate to ionized gas clusters from a source gas, the ionized gas clusters comprising at least one chalcogen and at least one electropositive element. A method ... | 05/03/2012 |
| 20120084612 | METHOD OF CONTROLLING A TEST MODE OF A CIRCUIT A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other out... | 04/05/2012 |
| 20120081974 | INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capaci... | 04/05/2012 |
| 20120081967 | METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY CELLS BASED ON PROGRAMMING OF PROXIMATE MEMORY CELLS A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proxim... | 04/05/2012 |
| 20120072682 | DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode dete... | 03/22/2012 |
| 20120070988 | METHODS AND APPARATUSES FACILITATING FLUID FLOW INTO VIA HOLES, VENTS, AND OTHER OPENINGS COMMUNICATING WITH SURFACES OF SUBSTRATES OF SEMICONDUCTOR DEVICE COMPONENTS A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or at least one aperture.... | 03/22/2012 |
| 20120070973 | Methods of Forming Diodes Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along... | 03/22/2012 |
| 20120070959 | MICROELECTRONIC DEVICE WAFERS AND METHODS OF MANUFACTURING Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etchi... | 03/22/2012 |
| 20120070955 | Methods of Forming Conductive Contacts to Source/Drain Regions and Methods of Forming Local Interconnects The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect ... | 03/22/2012 |
| 20120070768 | RETICLES WITH SUBDIVIDED BLOCKING REGIONS AND METHODS OF FABRICATION Methods for designing, fabricating, and using attenuated phase shift reticles, or photomasks are disclosed. Methods are also disclosed for subdividing the radiation blocking regions of previously fabricated reticles of previously existing designs. The methods may includ... | 03/22/2012 |
| 20120069691 | BLOCK REPAIR SCHEME Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further emb... | 03/22/2012 |
| 20120069675 | REDUCING NOISE IN SEMICONDUCTOR DEVICES The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sens... | 03/22/2012 |
| 20120069659 | MEMORY WITH INTERLEAVED READ AND REDUNDANT COLUMNS Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of col... | 03/22/2012 |
| 20120069658 | METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry i... | 03/22/2012 |
| 20120069648 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an ant... | 03/22/2012 |
| 20120069647 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more SIT memory cell structures comprise a STT stack including; a pinned ferromagnetic material in contact with an antiferromagnetic material; a tunneling barrier material positio... | 03/22/2012 |
| 20120069646 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an ant... | 03/22/2012 |
| 20120069624 | REACTIVE METAL IMPLATED OXIDE BASED MEMORY Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting... | 03/22/2012 |
| 20120069060 | NOR-BASED GRAYSCALE FOR A DIGITAL DISPLAY A digital display provides pulse-width-modulated pixel waveforms by applying a wired-NOR function to selected bits of stored image data. Image bits are selected according to a digital sequence and the wired-NOR function results in a trigger signal that may be used to sw... | 03/22/2012 |
| 20120068872 | METHODS OF QUANTIZING SIGNALS USING VARIABLE REFERENCE SIGNALS Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on... | 03/22/2012 |
