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| Application No. | Application Title | Issue Date |
| 20120051121 | POWER GATEABLE RETENTION STORAGE ELEMENT A method, electronic device, and system are provided in which data is stored in a gateable retention storage element. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus which includes a sili... | 03/01/2012 |
| 20120025276 | TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING A PN JUNCTION BASED ON SILICON/GERMANIUM MATERIALS By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a proc... | 02/02/2012 |
| 20120003832 | METHOD OF REDUCING EROSION OF A METAL CAP LAYER DURING VIA PATTERNING IN SEMICONDUCTOR DEVICES During the patterning of via openings in sophisticated metallization systems of semiconductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to ... | 01/05/2012 |
| 20110237161 | METHOD AND SYSTEM FOR CONTROLLING CHEMICAL MECHANICAL POLISHING BY CONTROLLABLY MOVING A SLURRY OUTLET A system and a method of operating a chemical mechanical polishing (CMP) system comprises a slurry delivering unit configured for locally varying the supply of slurry while polishing the substrate. To this end, the slurry delivering unit may comprise at least one slurry... | 09/29/2011 |
| 20110223732 | THRESHOLD ADJUSTMENT FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extensi... | 09/15/2011 |
| 20110218660 | METHOD AND APPARATUS FOR AUTOMATED FAB CONTROL A method, apparatus, and a system for prioritizing processing of a workpiece is provided. At least one workpiece is processed. A tag associated with the workpiece is provided. The tag includes process priority data for determining an order relating to processing the wor... | 09/08/2011 |
| 20110201165 | CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND NON-CONFORMAL METAL SILICIDE REGIONS A non-conformal metal silicide in a transistor of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation proce... | 08/18/2011 |
| 20110183477 | SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective ope... | 07/28/2011 |
| 20110117723 | NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO ALIGNMENT AND FEATURE SHAPING By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required i... | 05/19/2011 |
| 20110104878 | SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be in... | 05/05/2011 |
| 20110020958 | METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERISTICS DURING FABRICATION OF VIAS OF INTERCONNECT STRUCTURES By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective open... | 01/27/2011 |
| 20100252866 | TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG A CRYSTALLOGRAPHIC ORIENTATION WITH INCREASED CHARGE CARRIER MOBILITY By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one i... | 10/07/2010 |
| 20100237431 | REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer o... | 09/23/2010 |
| 20100187635 | SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be in... | 07/29/2010 |
| 20100187629 | TENSILE STRAIN SOURCE USING SILICON/GERMANIUM IN GLOBALLY STRAINED SILICON By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/ger... | 07/29/2010 |
| 20100181619 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised dra... | 07/22/2010 |
| 20100155850 | TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor mater... | 06/24/2010 |
| 20100155727 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accompli... | 06/24/2010 |
| 20100058048 | Profile Adjustment Module For Use With Data Processing System A profile adjustment module which enables customization of the profiles within a computer system. The profile adjustment module enables gaming or entertainment enthusiast or customers an easy-to-use interface to tune their personal computer for maximum performance for a... | 03/04/2010 |
| 20100024724 | APPARATUS AND METHOD FOR REMOVING BUBBLES FROM A PROCESS LIQUID The present invention is directed to methods and apparatuses for removing bubbles from a process liquid. The process liquid can comprise a plating solution used in a plating tool. The process liquid is supplied to a tank. A plurality of streams of the process liquid are... | 02/04/2010 |
| 20100010798 | Modeling of variations in drain-induced barrier lowering (DIBL) The present method is a method of modeling Drain-Induced Barrier Lowering (DIBL) in a transistor model, the transistor model being based on a MOSFET transistor. The transistor model includes a base, a source, a drain, a gate, and a gate terminal. In the present method, ... | 01/14/2010 |
| 20100009536 | MULTILAYER LOW REFLECTIVITY HARD MASK AND PROCESS THEREFOR A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer ... | 01/14/2010 |
| 20090305498 | SEMICONDUCTOR DEVICE COMPRISING A COPPER ALLOY AS A BARRIER LAYER IN A COPPER METALLIZATION LAYER By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambien... | 12/10/2009 |
| 20090300288 | Write Combining Cache with Pipelined Synchronization Systems and methods for pipelined synchronization in a write-combining cache are described herein. An embodiment to transmit data to a memory to enable pipelined synchronization of a cache includes obtaining a plurality of synchronization events for transactions with sa... | 12/03/2009 |
| 20090295819 | Floating Point Texture Filtering Using Unsigned Linear Interpolators and Block Normalizations Apparatus and systems utilizing fixed point filtering to perform floating point texture filtering. A texture pipe unit consisting of a texture addressing unit, texture cache unit, and texture filter unit accepts texture requests for a specified pixel from a resource and... | 12/03/2009 |
| 20090294896 | SHALLOW TRENCH ISOLATION PROCESS UTILIZING DIFFERENTIAL LINERS A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce str... | 12/03/2009 |
| 20090292385 | AUTOMATED THROUGHPUT CONTROL SYSTEM AND METHOD OF OPERATING THE SAME An automated throughput control system and method is provided. By gathering tool specific information of a plurality of process tools on entity level, appropriate throughput related performance characteristics may be calculated with high statistical significance during ... | 11/26/2009 |
| 20090289949 | Dynamically Configurable Bilinear Filtering System Apparatus and methods for a bilinear filter system comprising a pre-formatter module, a bilinear module, an accumulator module, and a format module. The pre-formatter module is configured to receive texel data and convert it to a normalized fixed point format. The bilin... | 11/26/2009 |
| 20090262570 | Giant magnetoresistance (GMR) memory device The present magnetic memory device includes a pinned ferromagnetic layer, and a switchable ferromagnetic layer, the memory device being programmable to have a first programmed state wherein the resistance of the device is at a first level, a second programmed state wher... | 10/22/2009 |
| 20090236667 | SEMICONDUCTOR DEVICE COMPRISING ISOLATION TRENCHES INDUCING DIFFERENT TYPES OF STRAIN By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed ... | 09/24/2009 |
| 20090181537 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A... | 07/16/2009 |
| 20090172675 | Re-Entrant Atomic Signaling Systems for context switching a requestor engine during an atomic process without corrupting the atomic process. Typically an atomic process cannot be interrupted prior to completion and if it is interrupted, the process will terminated abnormally resulting in a corrupt... | 07/02/2009 |
| 20090064149 | Latency coverage and adoption to multiprocessor test generator template creation A multi-core multi-node processor system has a plurality of multiprocessor nodes, each including a plurality of microprocessor cores. The plurality of microprocessor nodes and cores are connected and form a transactional communication network. The multi-core multi-node ... | 03/05/2009 |
| 20090047770 | METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is d... | 02/19/2009 |
| 20090021280 | Method and test system for determining gate-to-body current in a floating body FET In one disclosed embodiment, the present method for determining a gate-to-body current for a floating body FET comprises measuring at least three unique gate-to-body currents corresponding to at least three unique body-tied FET structures, determining at least three uni... | 01/22/2009 |
| 20090020754 | Test structure for determining gate-to-body tunneling current in a floating body FET In one disclosed embodiment, the present test structure for determining gate-to-body current in a floating body FET includes a floating body FET situated over a semiconductor layer, where the floating body FET includes a first gate and first and second source/drain regi... | 01/22/2009 |
| 20090011524 | Method for determining suitability of a resist in semiconductor wafer fabrication In one disclosed embodiment, the present method for determining resist suitability for semiconductor wafer fabrication comprises forming a layer of resist over a semiconductor wafer, exposing the layer of resist to patterned radiation, and determining resist suitability... | 01/08/2009 |
| 20090001138 | Method for preventing void formation in a solder joint In one disclosed embodiment, the present method for preventing void formation in a solder joint formed between two metallic surfaces includes forming at least one slit in a layer of solder to form a slit solder layer, positioning the slit solder layer between the two me... | 01/01/2009 |
| 20080318369 | SOI DEVICE WITH CHARGING PROTECTION AND METHODS OF MAKING SAME The present invention is directed to an SOI device with charging protection and methods of making same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes ... | 12/25/2008 |
| 20080305617 | Method for depositing a conductive capping layer on metal lines In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The appli... | 12/11/2008 |
