US Class714/727Boundary scan
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504
), only reduced pin JTAG devices (506
), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502
) between the substrate (408
) and a JTAG controller (404
). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.