US Classes438/404, Total dielectric isolation257/E21.54Making of isolation regions between components (EPO)
- 201010527260.6 CN 10/29/2010
Issued Patent Number:8232178
A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S11
); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S12
); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S13
); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S14
). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.