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US Patent Application 20120105118 - DELAY LOCKED LOOP AND INTEGRATED CIRCUIT INCLUDING THE SAME

Application 20120105118 Filed on December 29, 2010. Published on May 3, 2012

Inventor

US Class

327/158With variable delay means

Foreign Documents

  • 10-2010-0105440 KR 10/27/2010

International Class

H03L 7/06

Issued Patent Number:

8258840


Abstract text


A delay locked loop includes a first delay unit configured to output an output clock by delaying an input clock by a delay; a replica delay unit configured to output a feedback clock by delaying the output clock with a delay equal to a sum of a first delay amount for a first operational frequency of the delayed locked loop and an additional delay amount for a second operational frequency of the delayed locked loop, wherein the second operational frequency is lower than the first operational frequency; and a delay amount control unit configured to control the delay of the first delay unit by comparing a phase of the input clock with a phase of the feedback clock.

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