InventorsUS Classes326/16, WITH TEST FACILITATING FEATURE326/104FUNCTION OF AND, OR, NAND, NOR, OR NOTForeign Documents- 10-2009-0131995 KR 12/28/2009
International Classes H03K 19/00 H03K 19/20 Issued Patent Number:7969180
Abstract textA semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode. | 
