InventorsAssigneeUS Classes257/3, With means to localize region of conduction (e.g., "pore" structure)257/368, Insulated gate field effect transistor in integrated circuit257/913, WITH MEANS TO ABSORB OR LOCALIZE UNWANTED IMPURITIES OR DEFECTS FROM SEMICONDUCTORS (E.G., HEAVY METAL GETTERING)438/310, Gettering of semiconductor substrate257/E23.137Including materials for absorbing or reacting with moisture or other undesired substances, e.g., getters (EPO)Attorney, Agent or FirmInternational ClassesH01L 29/04H01L 21/8222 Issued Patent Number:7564082Abstract textOne aspect of this disclosure relates to a semiconductor structure, comprising a gettering region proximate to a device region in a semiconductor wafer. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids through a surface transformation process. Each of the voids has an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region. The structure includes a transistor formed using the device region. The transistor includes a gate dielectric over the device region, a gate over the gate dielectric, and a first diffusion region and a second diffusion region formed in the device region. The first and second diffusion regions are separated by a channel region formed in the device region between the gate and the proximity gettering region. |
| ||||||||||||||