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| Application No. | Application Title | Issue Date |
| 20070260927 | METHODS, SYSTEMS AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING AN INTERNET PROTOCOL BASED DEVICE HEALTH CHECK Methods, systems and computer program products provide an IP based device health check. The methods include initiating a health check to be performed at a customer location. The results of the health check are received and stored as an install state. A current state tha... | 11/08/2007 |
| 20070260928 | System and method for engineered decoupling in a development environment A system and method for providing engineered decoupling in a development environment. According to an embodiment of the invention, an infrastructure framework is configured to process one or more service requests from a frontend application, an actual runtime engine is ... | 11/08/2007 |
| 20070260929 | Pluggable debugging interface for graphical notation diagrams A low-level process, which was mapped from a high-level graphical notation diagram, is debugged using the high-level graphical notation diagram. To debug the low-level process, a debugging interface allows a user to set and track breakpoints and other debug events from ... | 11/08/2007 |
| 20070260930 | Selective alteration of shell utility return code In a shell utility computer program code configured to cause at least one computer processor comprising one host computer system to connect to a second host computer system, and to cause the second host computer system to execute at least one command provided to one hos... | 11/08/2007 |
| 20070260931 | Merging multi-line log entries A system and method for building merged events from log entries received from multiple devices. Multiple log events generally contribute to a single merged event. In the described embodiment, the mapping module receives log entries associated with specific merged events... | 11/08/2007 |
| 20070260932 | Event log management system The present invention is an event log management system and method for monitoring the reliability of test systems. An event log management system includes a data store which stores at least one tester configuration file, a hardware independent event capture function whi... | 11/08/2007 |
| 20070260933 | Recording analog characteristics of data from a data line in a protocol analyzer This disclosure relates to systems and methods for recording analog characteristics of data. In one example embodiment, a method for recording and outputting a waveform in a protocol analyzer includes receiving analog data, converting the analog data to digital data tha... | 11/08/2007 |
| 20070260934 | Automated hardware parity and parity error generation technique for high availability integrated circuits A technique wherein High Availability (HA) hardware is used to automatically validate control and configuration registers, e.g. automatically generate parity, detect parity errors, and report errors within software-written configuration and control registers of ASIC and... | 11/08/2007 |
| 20070260935 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR COMPENSATING FOR DISRUPTION CAUSED BY TRACE ENABLEMENT A method for compensating for disruption caused by trace enablement is provided. The method includes receiving a selected target to run a program, receiving a selected program that has been identified as having a problem, and receiving a selected trace type. The method ... | 11/08/2007 |
| 20070260936 | Systems and methods for assigning identifiers to test results for devices within a group There are disclosed systems and methods for coordinating test results of devices within a group. In an embodiment, the system may include code to assign identifiers to test results of a first test execution, receive a user-specified beginning point, and assign identifie... | 11/08/2007 |
| 20070260937 | Systems and methods for selectively logging test data There are disclosed systems and methods for selectively logging test data. In an embodiment, a system includes code to monitor test data generated by a plurality of devices and to generate statistics related to the test data; and code to in response to the statistics re... | 11/08/2007 |
| 20070260938 | Method, code, and apparatus for logging test results In one embodiment, a method for logging test results, has steps for: A) accessing a stream of test data associated with a tester performing tests on a number of devices under test; B) selecting items of the test data to be logged to a data store, the selecting being per... | 11/08/2007 |
| 20070260939 | ERROR FILTERING IN FAULT TOLERANT COMPUTING SYSTEMS A system for tolerating a single event fault in an electronic circuit is disclosed. The system includes a main processor, a fault detection processor responsive to the main processor, the fault detection processor further comprising a voter logic circuit, three or more ... | 11/08/2007 |
| 20070260940 | Automatic protection switching and error signal processing coordination apparatus and methods Automatic Protection Switching (APS) and error signal processing coordination apparatus and methods are disclosed. If a communication module that enables communication signals and error signals to be exchanged with a remote communication module is configured in an APS p... | 11/08/2007 |
| 20070260941 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD An information processing apparatus detects an error which occurred in a system and stores a system status that the error occurred in association with error information indicating the error. The information processing apparatus outputs guidance information according to ... | 11/08/2007 |
| 20070260942 | Transactional memory in out-of-order processors Methods and apparatus to provide transactional memory execution in out-of-order processors are described. In one embodiment, a stored value corresponds to the number of transactional memory access requests that are uncommitted. The stored value may be used to provide ne... | 11/08/2007 |
| 20070260943 | Proactive server-side error subsystem for interactive objects A software error subsystem is provided that can log, report, and may optionally correct defective interactive objects in a virtual game environment. The subsystem may form part of a larger and more general logging and error catching system. By automatically correcting c... | 11/08/2007 |
| 20070260944 | Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. A means for decoding LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain... | 11/08/2007 |
| 20070260945 | Method for accuracy improvement allowing chip-by-chip measurement correction A method for allowing measurement corrections on a chip-by-chip basis. Error correction values are generated responsive to the input value to a circuit of the calibrated integrated circuit chip and to a measured value from the circuit of the calibrated integrated circui... | 11/08/2007 |
| 20070260946 | Nonvolatile memory device comprising a programming and deletion checking option A method and circuitry for checking the programming (P) and deletion (L) operations of memory cells (5) in a nonvolatile memory device (1). Parallel to the programming (P) or deletion (L) operations of the actual memory cells (5) the respective prog... | 11/08/2007 |
| 20070260947 | MEASURING APPARATUS, MEASURING METHOD, TESTING APPARATUS, TESTING METHOD, AND ELECTRONIC DEVICE There is provided a measuring apparatus for measuring a signal-under-test, having a comparator for sequentially comparing voltage values of the signal-under-test with a threshold voltage value fed thereto at timing of strobe signals sequentially fed thereto, a strobe ti... | 11/08/2007 |
| 20070260948 | Driver IC and inspection method for driver IC and output device A driver IC including: a plurality of output pads; and a plurality of signal switch circuits, each of the signal circuits being provided on one of signal paths respectively connected to the output pads, wherein each of the signal switch circuits switches between a first... | 11/08/2007 |
| 20070260949 | Trading propensity-based clustering of circuit elements in a circuit design An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based... | 11/08/2007 |
| 20070260950 | Method and apparatus for testing a data processing system A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of th... | 11/08/2007 |
| 20070260951 | Uncompromised standard input set-up time with improved enable input set-up time characteristics in a storage circuit A method and/or system of uncompromised standard input set-up time with improved enable input set-up time characteristics in a storage circuit are disclosed. In one embodiment, a storage circuit includes a master latch coupled to a slave latch where each undergoes data ... | 11/08/2007 |
| 20070260952 | DFT TECHNIQUES TO REDUCE TEST TIME AND POWER FOR SoCs A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all flip-flops in the core. The partial residual test mode spans across a subset of the cores and allows to bound the... | 11/08/2007 |
| 20070260953 | Scan test An electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of th... | 11/08/2007 |
| 20070260954 | Integrated circuit with low-power built-in self-test logic An integrated circuit with low-power built-in self-test logic (“IC-LPBIST”) is disclosed. The IC-LPBIST may include combinational logic and a loading circuit enabled to load a shift test pattern of data into the loading circuit without powering the combinational log... | 11/08/2007 |
| 20070260955 | TEST AUXILIARY DEVICE IN A MEMORY MODULE Methods and apparatus for applying a test pattern to cells in a memory module. A test auxiliary device in a memory module contains a test pattern selection device for selecting a test pattern from at least two elementary M-bit test patterns. The test pattern is applied ... | 11/08/2007 |
| 20070260956 | METHOD AND SYSTEM FOR SUPPORTING MULTIPLE HYBRID AUTOMATIC REPEAT REQUEST PROCESSES PER TRANSMISSION TIME INTERVAL A method and system for supporting multiple hybrid automatic repeat request (H-ARQ) processes per transmission time interval (TTI) are disclosed. A transmitter and a receiver include a plurality of H-ARQ processes to transmit and receive multiple transport blocks (TBs) ... | 11/08/2007 |
| 20070260957 | Encoded transmission Significant improvement in Raptor codes and punctured LDPC codes are obtainable by use of the invention. In both a transmission scheme for Raptor-encoded or LDPC-encoded information, a dynamic adjustment approach is employed. A fraction of a codeword or information fram... | 11/08/2007 |
| 20070260958 | WIRELESS COMMUNICATION METHOD AND SYSTEM FOR BIT INTERLEAVED CODED MODULATION AND ITERATIVE DECODING A wireless communication method and system for performing bit-interleaved coded modulation and iterative decoding. The system includes a transmitter and a receiver. The transmitter encodes incoming bits to generate coded bits, punctures the coded bits in accordance with... | 11/08/2007 |
| 20070260959 | LOG-LIKELYHOOD RATIO (LLR) COMPUTATION USING PIECEWISE LINEAR APPROXIMATION OF LLR FUNCTIONS Techniques for efficiently and accurately computing log-likelihood ratio (LLRs) for code bits are described. A set of code bits may be mapped to a modulation symbol in a signal constellation. Different code bits in the set may be associated with different LLR functions.... | 11/08/2007 |
| 20070260960 | ERROR CORRECTION SYSTEM AND RELATED METHOD THEREOF Disclosed is an error correction system, which comprises: a demodulator for receiving and demodulating raw data to generate an ECC block; an on the fly PI syndrome generator, coupled to the demodulator, for generating a PI syndrome according to the ECC block from the de... | 11/08/2007 |
| 20070260961 | ERROR CORRECTION SYSTEM AND RELATED METHOD THEREOF Disclosed is an error correction system, comprising: a demodulator for receiving and demodulating raw data to generate an ECC block; an on the fly PI ECC decoder, coupled to the demodulator, for performing a PI ECC operation on the ECC block; a data buffer, for storing ... | 11/08/2007 |
| 20070260962 | Methods and apparatus for a memory device with self-healing reference bits A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set... | 11/08/2007 |
| 20070260963 | ERROR CORRECTION SYSTEM AND RELATED METHOD THEREOF Disclosed is an error correction system, comprising: a demodulator for receiving and demodulating raw data to generate an ECC block; an on the fly EDC check device for performing an EDC operation according to data of the ECC block from the demodulator to generate an EDC... | 11/08/2007 |
| 20070260964 | Semiconductor memory In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector s... | 11/08/2007 |
| 20070260965 | Error detection in physical interfaces for point-to-point communications between integrated circuits An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a rece... | 11/08/2007 |
| 20070260966 | Error Correction Method and Apparatus for Low Density Parity Check An apparatus for and a method of correcting an error using a low density parity check (LDPC) matrix. A resultant matrix is generated by performing XOR and modular 2 operations with respect to the LDPC matrix and a code word vector and a number of 1 bits in the resultant... | 11/08/2007 |
